Control and configuration registers
| TX_ENA | write this bit to enable the bitscrambler tx |
| TX_PAUSE | write this bit to pause the bitscrambler tx core |
| TX_HALT | write this bit to halt the bitscrambler tx core |
| TX_EOF_MODE | write this bit to ser the bitscrambler tx core EOF signal generating mode which is combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0 counter by write peripheral buffer |
| TX_COND_MODE | write this bit to specify the LOOP instruction condition mode of bitscrambler tx core, 0: use the little than operator to get the condition, 1: use not equal operator to get the condition |
| TX_FETCH_MODE | write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch by reset, 1: fetch by instrutions |
| TX_HALT_MODE | write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0: wait write data back done, , 1: ignore write data back |
| TX_RD_DUMMY | write this bit to set the bitscrambler tx core read data mode when EOF received.0: wait read data, 1: ignore read data |
| TX_FIFO_RST | write this bit to reset the bitscrambler tx fifo |